Traditionally, integrated circuit (IC) chips are packaged individually as single dies. Chip are packaged one at a time after the front-end processing of a semiconductor substrate is complete and the substrate is singulated into individual dies. In contrast, front-end processing steps for IC fabrication allow one to fabricate a number of chips simultaneously on a single wafer, thereby increasing throughput and cost-effectiveness. Moreover, the shrinking geometries of integrated circuits present a further limitation to traditional packaging techniques. The need for an increased density of conductive leads requires a reduction in connector pitch, both in packages and in printed circuit boards (PCB). This scaling down of geometry approaches the limits of existing packaging technology and increases packaging costs.
The challenges of shrinking geometries have been addressed by the development of ball grid arrays (BGA). BGA is an alternative packaging method that allows one to contact IC chip pads with solder balls that are later attached to printed circuit boards. The use of solder balls reduces the length of the conductive legs contacting the die, thereby lowering the parasitics of the legs at higher operating frequencies and lowering energy consumption.
Wafer level packaging (WLP) methods also address the limitations of traditional packaging techniques. WLP employs some of the processing steps used in front-end processing, such as fabrication of contacts to IC chip pads and to package many dies simultaneously. WLP can include making legs on the upper surfaces of a chip, using front-end technology. One can, therefore, simultaneously package all the chips on a single substrate cost-effectively. However, certain WLP processes have the disadvantage of packaging bad dies as well as good dies.
Three fabrication elements are needed for packaging an integrated circuit: an interconnect element between chip and package; a protective layer on the active side of the chip, such as a polyimide layer; and, in the case in which chips have pads with a low pitch, e.g. 150 μm, a redistribution of chip pads in an area array having a larger pitch, e.g. 800 μm, to allow the use of inexpensive circuit boards having larger pitches. Small footprints are achieved when the package is the same size as the chip.
A difficulty in wafer level processing results from the integration of materials having different thermal expansion coefficients. For example, a semiconductor chip is usually fabricated from silicon, which has a coefficient of thermal expansion (CTE) of approximately 3×10−6/K. A circuit board, on the other hand, has a much higher CTE of approximately 15-18×10−6/K. Chips and boards undergo thermal cycling during reliability testing. For example, a standardized reliability test requires cycling two times an hour between −40° C. and 125° C. During such cycling, stress is induced, especially in the case of large chips. The board, with its higher CTE, expands more than the chip during heating. Thermal cycling can, therefore, lead to bowing of the board, excessive stresses on the chip, and, possibly, destruction of the chip and/or board.
Historically, large chips are packaged with long legs or leads (leadframe packages). These long legs can absorb stress resulting from CTE mismatch. However, this approach becomes problematic as pad pitches decrease, thereby also decreasing the leg pitch requirements to dimensions that are difficult to achieve.
An alternative approach, in which chips are soldered directly to the circuit board, fails to provide the necessary elasticity. A solder bump for connecting a chip to a PCB can be destroyed during soldering, thermal cycling, or burn-in because of CTE mismatch and the non-compliance of the solder bump. This presents a reliability risk, especially for large chips, i.e. chips having solder balls at a distance greater than 5 mm from a neutral point. One solution is to provide a polymeric underfill, thereby enabling the chip to adhere to the PCB. The underfill serves as a stress absorber. A packaged die is soldered to the board, after which underfill is applied to the package and hardened. This resulting structure reduces the stress on the legs or solder balls. The underfill, however is hard and will tend to absorb stress, thereby causing the board to bend. Commonly used underfill processes do not fulfill the need for short process time as well as low process cost.